Simple CPU (8-bit) - VHDL/FPGA
Architected and deployed a complete 8-bit CPU on Altera DE FPGA using VHDL...
- Designed register file with 8 general-purpose registers
- Implemented FSM for instruction cycle control
- Built ALUs supporting ADD, SUB, and logic ops
- Validated execution with Quartus + ModelSim
VHDL, FPGA, Quartus, ModelSim